An MOS transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. In the latter configuration, constriction occurs at high current flows, an effect that places substantial constraints on the design of a transistor intended for operation under such conditions.
A trench gate of a DMOS device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, "Trench DMOS Transistor Technology for High-Current (100 A Range) Switching," in Solid-State Electronics, 1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS-gated devices.
Self-aligned trenches in an MOS device allow the distance between source and trench gate contacts to be substantially reduced, enabling a beneficial increase in packing density for VLSI fabrication. U.S. Pat. No. 5,393,704 to Huang et al., the disclosure of which is incorporated herein by reference, describes a method of forming in and on a substrate a self-aligned trench contact for a device region that includes gate electrodes on the semiconductor substrate, source/drain regions within the substrate, and spacers on the gate electrode sidewalls. The sidewall spacers are used as a mask to provide an opening to the substrate where the trench contact is to be formed.
U.S. Pat. No. 5,716,886 to Wen, the disclosure of which is incorporated herein by reference, describes a method of fabricating a high-voltage MOS device in which a silicon nitride layer is used as a mask to form trench type source/drain regions in a substrate. The trench source/drain regions contain two conductive layers; portions of the same two conductive layers are included in a gate on the substrate surface.
U.S. Pat. No. 5,665,619 to Kwan et al., the disclosure of which is incorporated herein by reference, describes a method of fabricating a DMOS transistor having self-aligned contact trenches that are etched through a masked oxide/nitride/oxide (ONO) sandwich on a silicon substrate. Gate polysilicon is deposited in the trenches and planarized with the nitride layer. The planarized polysilicon is covered with oxide; doping and four additional photolithographic masking steps are employed to form N+ source regions adjacent to the trenches and a P+ body ohmic content region between the source regions.
There is a continuing need for facilitating the fabrication of MOS-gated devices by a simplified process requiring fewer masking steps than are currently used. The present invention meets this need.